1. Field of the Invention
The present invention relates to systems and methods for implementing phase lock loop (PLL) circuits, and particularly for implementing PLL circuits to facilitate a wireless local area network (LAN). For example, the present invention finds application in the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard for wireless LANs.
2. Description of the Related Art
Wireless LAN (WLAN) standards (802.11b and 802.11g, for example) specify a transmit center frequency tolerance and chip clock frequency tolerances to be +/xe2x88x9225 ppm maximum. The two-way error between the receiver and transmitter can be up to +/xe2x88x9250 ppm and must be tracked by the receiver synchronization blocks. To establish a coherent reference at the receiver, the acquisition of frequency and timing is performed first. The maintenance of the coherent reference is achieved by tracking. Often the same synchronization mechanism is used to perform both acquisition and tracking. Among the most common architectures are the phase lock loop (PLL) for phase and frequency acquisition and tracking, and time-tracking loop (TTL) for chip timing acquisition and tracking. If the data is modulated directly on the carrier signal, or through a square-wave subcarrier, a suppressed carrier signal will result, and typically a special class of suppressed carrier tracking loops is then used.
There are different types of loops to perform chip level phase tracking. However, the performance of current PLLs, particularly those that operate with suppressed carrier signals, should take full advantage of the processing potential of the system. Current PLLs suffer squaring loss, lower symbol-to-noise ratios (SNR), and require more hardware resources than necessary to implement.
Accordingly, there is a need for PLLs with improved SNR and lower hardware requirements. Further, there is particularly a need for such PLLs in WLAN applications. The present invention meets these needs.
Embodiments of the invention include a PLL for suppressed carrier signals, such as with IEEE 802.11 standard signals, that takes advantage of symbol processing gain and extrapolates phase to chip-rate for effective phase error correction at the chip level. Embodiments of the invention perform well at high-frequency error and achieve fast phase and frequency acquisition. Further embodiments of the invention utilize an efficient and programmable phase discriminator.
The extrapolation is a novel approach that improves performance significantly. In addition, the loop utilizes a programmable mode decision directed phase discriminator that avoids squaring loss and takes advantage of known modulation types, for example BPSK or QPSK. Known loops, such as Costas and power loop work well with a suppressed carrier signal but exhibit the squaring loss and require more hardware (HW) than necessary.
Embodiments of the invention provide an efficient PLL implementation that allows fast frequency and phase synchronization and tracking, particularly in IEEE 802.11 or similar systems. The invention takes advantage of symbol rate processing, which affords an increased SNR and less hardware, and applies a chip-rate phase extrapolation technique to correct the phase between the symbol updates. The invention uses an efficient mode programmable decision directed phase discriminator for optimal noise performance and implementation.
A typical embodiment includes a demodulator receiving a phase error signal from a comparator at a chip rate and providing a phase error update over a symbol period of a symbol rate from the phase error signal wherein the chip rate is higher than the symbol rate. A phase discriminator produces a phase error output at the symbol rate from the phase error update based upon a signal modulation type. A loop filter produces one or more phase estimate parameters at a symbol rate from the phase error output and a numerically controlled oscillator (NCO) extrapolates a phase reference at a chip rate from the one or more phase estimate parameters at a symbol rate. The comparator produces the phase error signal to the demodulator based upon the phase reference and an incoming signal
The extrapolation process can be performed linearly or non-linearly based upon the phase estimate parameters produces by the loop filter. In an exemplary linear extrapolation, the loop filter can be implemented as a proportional and integral filter providing a phase change value and a phase rate value (e.g., a frequency error value) as the phase estimate parameters. A multiplexer can be used to load the phase estimate parameters into the NCO for extrapolation of the chip rate phase reference. Further, the NCO can include a look-up table for determining the phase reference as a sine and cosine function. The phase discriminator can include a slicing operation and is programmable to produce the phase error update based upon the modulation type. Typically, the modulation type is a biphase shift key (BPSK) modulation or a quadrature shift key (QPSK) modulation.
Further embodiments of the invention include a frequency estimator for estimating a frequency error and setting a loop filter accumulator state to the frequency error. The frequency estimator computes a decision directed cross-product discriminator to estimate the frequency error and applies it to the loop filter.
In still further embodiments, the loop filter can also include loop programmable bandwidth settings for a plurality of loop bandwidths. The loop bandwidth settings can alternately be programmed to an acquisition and a tracking loop bandwidth to improve the overall performance of the PLL.